1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating shallow trench isolation (STI).
2. Description of Related Art
High density plasma chemical vapor deposition (HDPCVD) systems have been developed that are capable of providing high quality dielectric layers at a deposition temperature significantly lower than the deposition temperature of a conventional CVD for forming dielectric layers. The HDPCVD dielectric layer has a superior density, moisture resistance, and planarization properties when compared to conventional CVD dielectric layers.
High-density plasma, which mediates deposition in HDPCVD systems, may be generated from a variety of sources, such as cyclotron resonance, inductively coupled plasma, helicon, and electrostatically shielded radio frequency. All of these plasma generation mechanisms allow for the addition and independent control of a bias sputter component in the deposition process.
One important feature of HDPCVD is to effectively fill a gap with the dielectric layer so that the surface is planarized. Nevertheless, there may be mechanisms of etching, sputtering, and deposition associated with the plasma technology. Therefore, a HDPCVD process for an oxide layer does not only include deposition of the oxide layer on the substrate surface, but also etching of the substrate surface and sputtering into the recess portion of the substrate.
FIG. 1 is a schematic diagram illustrating a cross-sectional view of a conventional STI structure. The diagram illustrates a silicon substrate 100, a silicon trench 104, a liner oxide layer 106, and a silicon nitride mask 102. Furthermore, a HDPCVD oxide layer 108 is formed to completely cover the entire silicon substrate 100 and to fill the silicon trench 104. As mentioned above, there are mechanisms of etching, sputtering, and deposition associated with the plasma technology. When the HDPCVD oxide layer 108 is deposited on the substrate 100, a bombardment etching may occur on the liner oxide layer 106, thus damaging the substrate 100 and sputtering into the recess portion of the substrate 100.